1. Field
Example embodiments relate to a method of fabricating a phase change RAM (PRAM) having a fullerene layer between a bottom electrode and a phase change layer.
2. Description of the Related Art
A phase change layer recording data in a phase change RAM (PRAM) may be in a crystal state and/or an amorphous state in accordance with a heating temperature and a cooling speed. When the phase change layer is in a crystal state, the resistance of a storage node may be relatively low, and when the phase change layer is in an amorphous state, the resistance of a storage node may be relatively high. The PRAM may be a non-volatile memory device recording and reading data, based on a resistance of current passing the phase change layer. The resistance of current passing the phase change layer may differ depending on whether the phase change layer of the PRAM may be in a crystal state and/or in an amorphous state.
In regards to PRAM, a reset current (Ireset) used to create a phase change layer with an amorphous structure may be relatively high. In order to increase an integration density of a typical PRAM, in which one cell may be composed of a storage node including one phase change layer and one transistor, sizes of the storage node and the transistor may be respectively reduced. When the size of the transistor is reduced, a maximum current of the transistor may decrease. When a reset current is higher than the maximum current of the transistor, data storage using the phase change and an increase in integration density of the PRAM may be relatively difficult unless the reset current of the PRAM is decreased.